System and method for testing and debugging analog circuits in a memory controller

ABSTRACT

A method and apparatus is presented for debugging and testing a memory controller. In one embodiment, a testing interface is presented for performing stuck-at testing. In a second embodiment, a testing interface is presented for observing clock timing in a memory controller.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation in part of U.S. application Ser. No.______ filed ______ and entitled ______, which is hereby incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION DESCRIPTION OF THE RELATED ART

Most modern electronic/computing systems include a memory and a memorycontroller. The memory controller generates the signals that control thereading and writing of information to and from the memory. In addition,in some implementations the memory controller interfaces the memory withthe other major parts of the electronic/computing system. The memorycontroller may be implemented as an integrated part of the system or thememory controller may be implemented on a removable interface.

Memory controllers may be provided separately for integration intosystem electronics. For example, conventional memory controllers mayinclude processors that can be built into an integrated circuit designand used to control data transfers to and from an external RAM deployedin an electronic/computing system. There are often several analogcircuits in these memory controllers and quite often the circuits don'tinclude test circuitry. Since there is no test circuitry the memorycontrollers are very difficult to debug.

In addition, given the way that many conventional memory controllers aredeployed even after circuitry is designed to test the memory controllerthere are no test ports (i.e., test hooks) to facilitate easyinterfacing and testing of the memory controller. One specific testingproblem includes clock timing. A significant amount of the digital logicon the memory controller receives a clock that came from off the memorycontroller (i.e., off chip) and is then processed through a delay line.Since the clock comes from an outside source the timing of the clock isunknown. As a result, testing is impacted because the timing and phaseof the clock is unknown.

Thus, there is a need for a method and apparatus for testing a memorycontroller. There is a need for generating known timing in a memorycontroller.

SUMMARY OF THE INVENTION

In accordance with the teachings of the present invention, a method andapparatus for testing a memory controller is presented. In oneembodiment, a circuit architecture is presented for interfacing with thememory controller and testing the memory controller. In addition, inaccordance with the teachings of the present invention, a method ispresented for providing a known clock to a memory controller.

In one embodiment the circuit architecture facilitates stuck-at testingon the analog portion of a memory controller. The circuit architectureincludes observation circuitry to view the clock inputs and outputs ofanalog delay lines on the memory controller, which greatly increases theability to debug the memory controller. In one embodiment, on-chipclocks (i.e., chips positioned on the memory controller) are multiplexedwith delay line clocks to provide a clock with a known phase fortesting.

As a result of the foregoing, a number of advantages may be realized.For example, stuck-at testing may be performed on the analog circuitryin a memory controller; memory controller delay line clocks may beobserved and debugged; and clocks with a known phase may be supplied tothe memory controller during test mode.

A memory controller interface, comprises a logic gate generating a firstoutput in response to a first high signal or a low signal; a firstmultiplexer coupled to the logic gate, the first multiplexer generatinga second output in response to the first output, in response to a secondhigh signal, and in response to a test clock signal; and a secondmultiplexer coupled to the first multiplexer, the second multiplexergenerating a third output signal in response to the second outputsignal, in response to a system clock signal and in response to a testmode signal.

A method of interfacing with a memory controller interface, comprisesthe steps of providing a delay line comprising an input for receivingdata, a plurality of delay elements including a last delay element and aplurality of registers associated with the delay elements; forcing thedelay line high; scanning first data the plurality of registers inresponse to forcing the delay line high; stepping a test clock signal inresponse to scanning the data into the selected registers; scanningsecond data out of the plurality of registers in response to steppingthe test clock signal; and comparing the second data in response toscanning the data out of the delay line registers and if the last delayelement is selected, forcing the delay line high in response tocomparing the second data.

A clock observation circuit for interfacing with a memory controller,the clock observation circuit comprises an input communicating an inputclock signal; a test access port generating a selection signal; an inputmultiplexer coupled the input and coupled to the first access port, theinput capable of communicating the input clock signal to a delay line inresponse the selection signal; an output multiplexer coupled to the testaccess port and capable of communicating an output clock signal from adelay line in response to communicating the input clock signal to thedelay line in response to the selection signal; an output coupled to theoutput multiplexer and generating the output clock signal in response toin response to communicating the output clock signal from the delayline.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 displays an architecture implemented in accordance with theteachings of the present invention.

FIG. 2 displays a detailed embodiment of a portion of the architecturedisplayed in FIG. 1.

FIG. 3 displays a high-level flow diagram detailing a method implementedin accordance with the teachings of the present invention.

FIG. 4 displays a detailed flow diagram detailing a method implementedin accordance with the teachings of the present invention.

FIG. 5 displays a timing interface to a delay line architectureimplemented in accordance with the teachings of the present invention.

DETAILED DESCRIPTION

While the present invention is described herein with reference toillustrative embodiments for particular applications, it should beunderstood that the invention is not limited thereto. Those havingordinary skill in the art and access to the teachings provided hereinwill recognize additional modifications, applications, and embodimentswithin the scope thereof and additional fields in which the presentinvention would be of significant utility.

In accordance with the teachings of the present invention, a circuitarchitecture is presented for testing a memory controller. In oneembodiment the circuit architecture is used to interface with a delayline. In addition, a circuit and method for providing a known clock to adelay line architecture is presented. FIG. 1 displays an architectureimplemented in accordance with the teachings of the present invention. Adelay line is shown as 100. A test interface to the delay line 100 isshown as 102.

FIG. 2 displays a detailed embodiment of a portion of the architecturedisplayed in FIG. 1. A delay line 200 is shown. The delay line 200includes several delay elements 202. Each delay element 202 is selectedusing a select input 204. In addition, each delay element 202 isconnected with a forward path 206, a reverse path 210, and a read path212. In one embodiment, signals propagate through the delay elements 202in the forward direction using the forward path 206. Signals returnthrough the delay elements 202 in a reverse direction using the reversepath 210 and the state of a delay element 202 is read using the readpath 212.

Memory storage elements such as flip-flops 214 are connected to the readpath 212. The memory storage elements (i.e., flip-flops 214) may bepositioned between each delay element 202 or the memory storage elements(i.e., flip-flops 214) may be evenly or unevenly spaced between thedelay elements 202 depending on the desired granularity of testing thatis required.

In one embodiment, delay line 200 is used to delay clocks going into andcoming out of a memory controller. During operation, a clock signal isapplied through input 201. Each delay element 202 provides a certainresolution so that an input signal conveyed on 201 may be changed basedon the delay elements 202 selected using the select 204. Each select 204determines if a signal passes through that delay element 202 or returnsthrough that delay element 202. For example, a technician may select thefourth delay element 202. As a result, a signal passes through theunselected delay elements and then returns back through the selecteddelay elements. As such, the delay elements 202 may be used to delay asignal such as a clock signal i.e., delay the phase of your clock. Theflip-flops 214 are storage elements. The Flip-flops 214 capture thevalue stored in the nearest delay element 202 and the value is thencompared to an expected value.

In one embodiment, stuck-at-testing is performed. A stuck-at-conditionoccurs when a delay element 202 maintains the same state. The registers(i.e., flip-flops 214) are strategically placed inside the delay line200 to capture the state of the delay line 200 while the select line 204is incremented from its lowest value to its highest value. Setting thedelay line 200 to a zero and incrementing through each delay element202, and then setting the delay line 200 to a one and incrementingthought each delay element 202 facilitates stuck-at testing withoutcompromising the functionality of the delay line 200 itself.

During operation a signal is introduced into the delay line 200 usinginput 201. Delay elements 202 are selected using the select input 204.The signal propagates through the forward path 206 until the signalreaches the delay element 202 selected by the select input 204. Thesignal then returns on the reverse path 210. In one embodiment, eachflip flop 214 prior to the delay element 202 selected using the selectinput 204, uses the read path 212 to store a value (i.e., 0 or 1) of thesignal. The values stored in the flip-flops 214 may then be analyzed totroubleshoot the delay elements 202. It should be appreciated that theflip-flops 214 may be positioned at different locations to get adifferent resolution of coverage.

A first multiplexer 218 is connected to the input 201. The firstmultiplexer 218 receives a scan mode signal 216 and a normal clockoperation signal 220. In one embodiment, the scan mode signal 216 placesa system in scan mode to perform testing such as scan mode testing andstuck-at testing. In one embodiment, the normal clock operation signal220 is a clock (i.e., timing signal) generated by the interfacecontroller.

A testing signal is conveyed on connection 219 between the firstmultiplexer 218 to a second multiplexer 221. The second multiplexer 221receive a test clock signal 222, a force high signal 224 and an output225 from a logic gate 226. The test clock signal 222 is an independentclock signal that can be introduced into the circuit architecture ofFIG. 1. The force high signal 224 is a signal for forcing a high signalon the input 201. The output 225 of the logic gate 226 provides anoutput of a logic gate such as AND gate 226. AND gate 226 receives aforce high signal 230 and a force low signal 228 as input. The selectionof the force hi signal 230 or force low signal 228 allows you to selectthe force hi 224 or the test clock input 222 of the multiplexer 221. Theforce high 224 may be set to a 1 or a 0 to provide a 1 or 0 on input 201and force the delay lines to all ones or to all zeros, respectively.

During operations, to force the input 201 hi and hence the delay line201 hi, the force hi 230 is set to 1 and the force low 228 is set to 0.As a result, the output of the multiplexer 221 (i.e., connection 219) ishigh, which is equivalent to 1. During operations to force the input 201low and hence the delay line 201 low, the force hi 230 is set to 0 andthe force low 228 is set to 1. As a result, the output of themultiplexer 221 (i.e., connection 219) is low, which is equivalent to 0.

FIG. 3 displays a flow diagram detailing a circuit architectureimplemented in accordance with the teachings of the present invention.FIG. 3 will be discussed in conjunction with FIG. 2. A signal isasserted on 216 to place the circuit into the scan mode. When the systemgoes into scan mode the multiplexer 221 is selected. The multiplexer 221has an input clock 222 and a force hi signal 224. To test for faults thedelay line 200 is forced high as stated at 300. The state of theflip-flops 214 are then stored as stated at 202. The delay line 100 isthen forced low as stated at 304. The state of the flip-flops 214 arethen stored as stated at 304. A comparison is then made between thestate of the flip-flops when the delay lines 214 were forced high andthe state of the flip-flops when the delay lines 200 were forced low.The comparison may be used to isolate a fault in the delay line 200 asstated at 310. Forcing the delay line 200 high and forcing the delayline 200 low provides information in both directions and then data canbe read for a stuck at 1 or stuck at 0 situation (i.e.,stuck-at-testing). This is a way of inserting a stuck-at configurationinto the delay line 200. When the delay line is forced into a specificstate the select lines are controlled so that a technician can stepthrough each element and during each step, capture the values in theassociated register.

FIG. 4 displays a detailed flow diagram detailing a method implementedin accordance with the teachings of the present invention. FIG. 4 isdescribed in conjunction with FIG. 1. At step 400 the delay line 200 isforced to 0. The scan mode signal 226 is set to 1 the force high signal230 is set to 0 and the force low signal 228 is set to 1. At step 402,data is scanned in to the delay line 200 to select registers selectingthe first element. At step 404, the test clock signal 222 is steppedforward and the delay line register (i.e., 224) is scanned out. At step406, a comparison is made of the data that is scanned out of the delayline 200. The tables provided below detailed the rules for thecomparison: If Force Low = 1: IF SEL < 7 SOUT=11111110; IF 6 < SEL < 15SOUT=11111010; IF 14 < SEL < 23 SOUT=11101010; IF SEL > 22SOUT=10101010; If Force Hi = 1: IF SEL < 4 SOUT=11111111; IF 3 < SEL <12 SOUT=11111101; IF 11 < SEL < 20 SOUT=11110101; IF 19 < SEL < 28SOUT=11010101; IF SEL > 27 SOUT=10101010.

At step 408, the data is tested to determine if the data compares. Ifthe data does not compare at 410 the test fails. If the data doescompare a test is made to determine if the last element has beenselected at 412. If the last element has not been selected at 414, datais scanned in to select additional registers by selecting the nextelement. Each element is selected by setting its select bit 204 to 0 andkeeping the lower select bits set to 1. An example, of selecting bit 5as shown by FIG. 1 is given by the followingsequence:SEL=31′b111111111111111111111111100000). The method then loopsback to step 404. At step 416, a comparison is made of the force highinput 230 to determine if the force high is set to 1. If the force highis set to 1 the test passes as shown at 420. If the force high is notset to 1, then at step 418 the delay line is forced to 1 by setting theforce high signal 230 to 1 and the force low signal 228 to 0.

FIG. 5 displays a clock observation circuit implemented in accordancewith the teachings of the present invention. In one embodiment, FIG. 2is a clock observation circuit. Memory interfaces 500, 504, 508, 512 and516 are shown. Each memory interfaces 500, 504, 508, 512 and 516includes a delay line 502, 506, 510, 514, and 518, respectively. Delaylines 502, 506, 510, 514, and 518 receive input on a delay line input501, 505, 509, 515, and 517, respectively. Delay lines 502, 506, 510,514, and 518 receive output on a delay line output 505, 507, 511, 515,and 519, respectively. Input access lines 520, 524, 528, 552 and 556access delay lines 502, 506, 510, 514 and 518, through delay line inputs501, 505, 509, 515 and 517. Output access lines 522, 526, 550, 554 and540 access delay lines 502, 506, 510, 514 and 518 through delay lineoutputs 505, 507, 511, 515 and 519, respectively. Buffers 570 arepositioned on delay line input (i.e., 501, 505, 509, 515, and 517),delay line output (i.e., 505, 507, 511, 515, and 519), input accesslines (i.e., 520, 524, 528, 552 and 556) and output access lines (i.e.,522, 526, 550, 554 and 540).

Input access lines 520, 524, 528, 552 and 556 convey signals betweenmultiplexer 546 and delay lines 502, 506, 510, 514 and 518. Multiplexers546 and 550 are connected through input 547. A clock input 552 isconnected to multiplexer 550. Test Access Ports (TAP) 542 and 544 areconnected to multiplexer 546. TAP 548 is connected to multiplexer 550.Output lines 522, 526, 550, 554 and 540 convey an output signal tomultiplexer 560. Multiplexers 560 and 564 are connected through output561. A clock output 566 is connected to multiplexer 564. Test AccessPorts (TAP) 556 and 558 are connected to multiplexer 560. TAP 562 isconnected to multiplexer 564.

In one embodiment, during operations, the architecture shown in FIG. 5is placed into test mode. Core clocks were multiplexed with the outputsof the delay lines. As a result, clocks with known phases are suppliedto the digital logic that received these clocks.

As shown in FIG. 5 different delay lines (i.e., 500, 504, 508, 512 and516) are presented. However, a multitude of other delay lines may bepresented. Each delay line has a buffer 570 a delay line input 501, 505,509, 515, and 517 that provides inputs to the delay lines (i.e., 500,504, 508, 512 and 516) and a buffer is placed on the delay line output505, 507, 511, 515, and 519, that provides an output signal path for thedelay lines (i.e., 500, 504, 508, 512 and 516). In one embodiment, asymmetrical buffer 570 is positioned on the delay line input (i.e., 501,505, 509, 515, and 517) and the delay line output (i.e., 505, 507, 511,515, and 519). Input access lines (i.e., 520, 524, 528, 552 and 556) tapinto the delay line input (i.e., 501, 505, 509, 515, and 517), andoutput access lines (i.e., 522, 526, 550, 554 and 540) tap into thedelay line output (i.e., 505, 507, 511, 515, and 519). In oneembodiment, symmetrical buffer 570 is positioned on Input access lines(i.e., 520, 524, 528, 552 and 556) and on output access lines (i.e.,522, 526, 550, 554 and 540).

Each delay line (500, 504, 508, 512 and 516) includes a buffer 570 onthe delay line input (i.e., 501, 505, 509, 515, and 517) and the delayline output (i.e., 505, 507, 511, 515, and 519). Input access lines(i.e., 520, 524, 528, 552 and 556) is used to tap into the delay lineinput (i.e., 501, 505, 509, 515, and 517), and output access lines(i.e., 522, 526, 550, 554 and 540) is used to tap into the delay lineoutput (i.e., 505, 507, 511, 515, and 519). Each of the input accesslines (i.e., 520, 524, 528, 552 and 556) and output access lines (i.e.,522, 526, 550, 554 and 540) are then sent through a multiplexer 546 and560 respectively, so that each access line (i.e., 520, 524, 528, 552,556, 522, 526, 550, 554 and 540) may be selected individually. Themulitplexer 546 is connected through the multiplexer 550 to an inputsignal conveyed on 552. The mulitplexer 560 is connected through themultiplexer 564 to an output signal conveyed on 566.

During operation, an input is conveyed on input 552 and an output isobserved on output 566. Therefore, during testing the clock signal maybe conveyed on the input 552 and then observed on the output 566.Therefore, a clock signal is observed before it enters the delay lineand then after it exits the delay line. Symmetric buffers are applieduniformly throughout the design to apply a comparable amount of delay onthe input and on the outputs. The two stage multiplexer, which comesfrom a test access port is used to select which delay line forobservation.

Thus, the present invention has been described herein with reference toa particular embodiment for a particular application. Those havingordinary skill in the art and access to the present teachings willrecognize additional modifications, applications, and embodiments withinthe scope thereof.

It is, therefore, intended by the appended claims to cover any and allsuch applications, modifications, and embodiments within the scope ofthe present invention.

1. A memory controller interface, comprising: a logic gate generating afirst output in response to a first high signal or a low signal; a firstmultiplexer coupled to the logic gate, the first multiplexer generatinga second output in response to the first output, in response to a secondhigh signal, and in response to a test clock signal; and a secondmultiplexer coupled to the first multiplexer, the second multiplexergenerating a third output signal in response to the second outputsignal, in response to a system clock signal and in response to a testmode signal.
 2. A memory controller interface as set forth in claim 1,further comprising an output coupled to the third output signal, theoutput for connecting the memory controller interface to a delay line,wherein the delay line is forced high in response to the third outputsignal or the delay line is forced low in response to the third outputsignal.
 3. A memory controller interface as set forth in claim 1, thememory controller interface further comprising a delay line coupled tothe second multiplexer, the delay line including a plurality of delayelements wherein at least one of the plurality of delay elements isforced high in response to the third output signal or at least one ofthe plurality of delay elements is forced low in response to the thirdoutput signal.
 4. A method of interfacing with a memory controllerinterface, comprising the steps of: providing a delay line comprising aninput for receiving data, a plurality of delay elements including a lastdelay element and a plurality of registers associated with the delayelements; forcing the delay line high; scanning first data the pluralityof registers in response to forcing the delay line high; stepping a testclock signal in response to scanning the data into the selectedregisters; scanning second data out of the plurality of registers inresponse to stepping the test clock signal; and comparing the seconddata in response to scanning the data out of the delay line registersand if the last delay element is selected, forcing the delay line highin response to comparing the second data.
 5. A method of interfacingwith a memory controller interface as set forth in claim 4, furthercomprising the steps of, scanning third data into the plurality ofregisters if the last element is not selected.
 6. A clock observationcircuit for interfacing with a memory controller, the clock observationcircuit comprising: an input communicating an input clock signal; a testaccess port generating a selection signal; an input multiplexer coupledthe input and coupled to the first access port, the input capable ofcommunicating the input clock signal to a delay line in response theselection signal; an output multiplexer coupled to the test access portand capable of communicating an output clock signal from a delay line inresponse to communicating the input clock signal to the delay line inresponse to the selection signal; an output coupled to the outputmultiplexer and generating the output clock signal in response to inresponse to communicating the output clock signal from the delay line.7. A clock observation circuit for interfacing with a memory controlleras set forth in claim 6, further comprising input access lines coupledbetween the input multiplexer and the delay line, the input access linescommunicating the input clock signal to a delay line in response theinput multiplexer communicating the input clock signal to a delay line.8. A clock observation circuit for interfacing with a memory controlleras set forth in claim 7, further comprising buffers on the input accesslines.
 9. A clock observation circuit for interfacing with a memorycontroller as set forth in claim 6, further comprising output accesslines coupled between the output multiplexer and the delay line, theoutput access line communicating the output clock signal to the outputmultiplexer from the delay line in response the delay line communicatingthe output clock signal.
 10. A clock observation circuit for interfacingwith a memory controller as set forth in claim 7, further comprisingbuffers on the output access lines.
 11. A clock observation circuit forinterfacing with a memory controller as set forth in claim 6, whereinthe input multiplexer is implemented with more than one inputmultiplexer.
 12. A clock observation circuit for interfacing with amemory controller as set forth in claim 6, wherein the input multiplexeris implemented with a first multiplexer and a second mulitplexerproviding input to the first multiplexer.
 13. A clock observationcircuit for interfacing with a memory controller as set forth in claim6, wherein the output multiplexer is implemented with more than oneoutput multiplexer.
 14. A clock observation circuit for interfacing witha memory controller as set forth in claim 6, wherein the outputmultiplexer is implemented with a first multiplexer and a secondmulitplexer providing output to the first multiplexer.
 15. A clockobservation circuit for interfacing with a memory controller as setforth in claim 6, first buffers are provided between the inputmultiplexer and the delay line and second buffers are provided betweenthe input multiplexer and the delay lines, wherein the first buffers andthe second buffers are equivalent.
 16. A clock observation circuit forinterfacing with a memory controller as set forth in claim 6, the testaccess port further comprising a first test access coupled to the inputmultiplexer and a second test access port coupled to the outputmultiplexer, the input selection signal further comprising a first inputselection signal communicated through the first test access port and asecond input selection signal communicated through the second testaccess port, the input multiplexer communicating the input clock signalto a delay line in response the first selection signal and the outputmultiplexer communicating the output clock signal from the delay line inresponse the second selection signal.